    M0 (Out In Vss Vss) NMOS_VTL w=360.0n l=50n as=3.78e-14 ad=3.78e-14 \
        ps=570.0n pd=570.0n ld=105n ls=105n m=1
    M1 (Out In Vdd Vdd) PMOS_VTL w=720.0n l=50n as=7.56e-14 ad=7.56e-14 \
        ps=930.0n pd=930.0n ld=105n ls=105n m=1
ends Project_4FOInverter_schematic
// End of subcircuit definition.
